Page 479 - 《软件学报》2025年第5期

苏浩然 等: SPARC 架构下低时延微内核进程间通信设计 2379

[24] Du D, Hua ZC, Xia YB, Zang BY, Chen HB. XPC: Architectural support for secure and efficient cross process call. In: Proc. of the 46th
Int’l Symp. on Computer Architecture. Phoenix: Association for Computing Machinery, 2019. 671–684. [doi: 10.1145/3307650.3322218]
[25] Mi ZY, Li DJ, Yang ZH, Wang XR, Chen HB. SkyBridge: Fast and secure inter-process communication for microkernels. In: Proc. of the
14th EuroSys Conf. Dresden: Association for Computing Machinery, 2019. 9. [doi: 10.1145/3302424.3303946]
2
[26] Courtaud C, Brandenburg BB. G(IP) C: Temporally isolated multiprocessor real-time IPC with server-to-server invocations. In: Proc. of
the 29th IEEE Real-time and Embedded Technology and Applications Symp. (RTAS). San Antonio: IEEE Computer Society, 2023.
276–288. [doi: 10.1109/RTAS58335.2023.00029]
[27] Bershad B, Anderson T, Lazowska E, Levy H. Lightweight remote procedure call. In: Proc. of the 12th ACM Symp. on Operating
Systems Principles. Litchfield Park: Association for Computing Machinery, 1989. 102–113. [doi: 10.1145/74850.74861]
[28] Xia YB, Du D, Hua ZC, Zang BY, Chen HB, Guan HB. Boosting inter-process communication with architectural support. ACM Trans.
on Computer Systems, 2021, 39(1–4): 6. [doi: 10.1145/3532861]
[29] Ford B, Lepreau J. Evolving mach 3.0 to a migrating thread model. In: Proc. of the 1994 USENIX Winter Technical Conf. San Francisco:
USENIX Association, 1994. 97–114.
[30] Levy HM. Capability-based Computer Systems. Bedford: Digital Press, 1984. 1–250. [doi: 10.1016/C2013-0-01290-X]
[31] Vilanova L, Jorda M, Navarro N, Etsion Y, Valero M. Direct inter-process communication (dIPC): Repurposing the CODOMs
architecture to accelerate IPC. In: Proc. of the 12th European Conf. on Computer Systems. Belgrade: Association for Computing
Machinery, 2017. 16–31. [doi: 10.1145/3064176.3064197]
[32] Watson RNM, Norton RM, Woodruff J, Moore SW, Neumann PG, Anderson J, Chisnall D, Davis B, Laurie B, Roe M, Dave NH, Gudka
K, Joannou A, Markettos AT, Maste E, Murdoch SJ, Rothwell C, Son SD, Vadera M. Fast protection-domain crossing in the CHERI
capability-system architecture. IEEE Micro, 2016, 36(5): 38–49. [doi: 10.1109/MM.2016.84]
[33] Klein G, Elphinstone K, Heiser G, Andronick J, Cock D, Derrin P, Elkaduwe D, Engelhardt K, Kolanski R, Norrish M, Sewell T, Tuch H,
Winwood S. seL4: Formal verification of an OS kernel. In: Proc. of the 22nd ACM SIGOPS Symp. on Operating Systems Principles. Big
Sky: Association for Computing Machinery, 2009. 207–220. [doi: 10.1145/1629575.1629596]
[34] Liedtke J. Improving IPC by kernel design. In: Proc. of the 14th ACM Symp. on Operating Systems Principles. Asheville: Association for
Computing Machinery, 1994. 175–188. [doi: 10.1145/168619.168633]
[35] Gu JY, Wu XY, Li WT, Liu N, Mi ZY, Xia YB, Chen HB. Harmonizing performance and isolation in microkernels with efficient intra-
kernel isolation and communication. In: Proc. of the 2020 USENIX Conf. on USENIX Annual Technical Conf. Berkeley: USENIX
Association, 2020. 27.
[36] Liedtke J. Lazy context switching algorithms for sparc-like processors. 1993. https://os.itec.kit.edu/downloads/publ_1993_liedtke_lazy-
context-switching.pdf
[37] Ottlik S. Reducing overhead in microkernel based multiserver operating systems through register banks [MS. Thesis]. Karlsruhe:
Karlsruhe Institute of Technology, 2010.
[38] Soares L, Stumm M. FlexSC: Flexible system call scheduling with exception-less system calls. In: Proc. of the 9th USENIX Conf. on
Operating Systems Design and Implementation. Vancouver: USENIX Association, 2010. 33–46.
[39] Ma Z, Qiao L, Yang MF, Li SF. Verification of operating system exception management for SPARC processor architecture. Ruan Jian
Xue Bao/Journal of Software, 2021, 32(6): 1631–1646 (in Chinese with English abstract). http://www.jos.org.cn/1000-9825/6241.htm
[doi: 10.13328/j.cnki.jos.006241]
[40] Black D, Golub DB, Julin DP, Rashid RF, Draves RP, Dean RW, Forin A, Barrera J, Tokuda H, Malan GR, Bohman D. Microkernel
operating system architecture and Mach. Journal of Information Processing, 1991, 14(4): 442−453.
[41] Elphinstone K, Heiser G. From L3 to seL4 what have we learnt in 20 years of L4 microkernels? In: Proc. of the 24th ACM Symp. on
Operating Systems Principles. Farminton: Association for Computing Machinery, 2013. 133–150. [doi: 10.1145/2517349.2522720]
[42] SPARC Int’l, Inc. The SPARC Architecture Manual: Version 8. Englewood Cliffs: Prentice-Hall, 1992. 202–204.
[43] Weaver DL. The SPARC Architecture Manual: Version 9. Englewood Cliffs: Prentice-Hall, 1994. xviii–xix.
[44] Hsieh WC, Kaashoek MF, Weihl WW. The persistent relevance of IPC performance: New techniques for reducing the IPC penalty. In:
Proc. of the 4th IEEE Workshop on Workstation Operating Systems. WWOS-III. Napa: IEEE Computer Society, 1993. 186–190. [doi: 10.
1109/WWOS.1993.348151]

附中文参考文献:
[14] 李钊, 李文新, 金田. 基于 BM3803 的操作系统移植和应用研究. 雷达科学与技术, 2016, 14(3): 311–316, 323. [doi: 10.3969/