Page 143 - 《软件学报》2024年第6期

谢汶兵 等: 二进制翻译技术综述 2719

[127] Pailoor S, Wang XY, Shacham H, Dillig I. Automated policy synthesis for system call sandboxing. Proc. of the ACM on Programming
Languages, 2020, 4(OOPSLA): 135. [doi: 10.1145/3428203]
[128] Rajagopalan M, Hiltunen MA, Jim T, Schlichting RD. System call monitoring using authenticated system calls. IEEE Trans. on
Dependable and Secure Computing, 2006, 3(3): 216–229. [doi: 10.1109/TDSC.2006.41]
[129] Xu H, Zhou YF, Ming J, Lyu M. Layered obfuscation: A taxonomy of software obfuscation techniques for layered security.
Cybersecurity, 2020, 3(1): 9. [doi: 10.1186/s42400-020-00049-3]
[130] Mohanta A, Saldanha A. Armoring and evasion: The anti-techniques. In: Mohanta A, Saldanha A, eds. Mohanta Abhijit Malware
Analysis and Detection Engineering: A Comprehensive Approach to Detect and Analyze Modern Malware. Berkeley: Apress, 2020.
691–720. [doi: 10.1007/978-1-4842-6193-4_19]
[131] Guanciale R. Protecting instruction set randomization from code reuse attacks. In: Proc. of the 23rd Nordic Conf. on Secure IT Systems.
Oslo: Springer, 2018. 421–436. [doi: 10.1007/978-3-030-03638-6_26]
[132] Professor GN. Proof-carrying code. In: van Tilborg HCA, Jajodia S, eds. Encyclopedia of Cryptography and Security. Boston: Springer,
2011. 984–986. [doi: 10.1007/978-1-4419-5906-5_864]
[133] Chen W, Chen D, Wang ZY. An approach to minimizing the interpretation overhead in dynamic binary translation. The Journal of
Supercomputing, 2012, 61(3): 804–825. [doi: 10.1007/s11227-011-0636-y]
[134] Shen BY, You JY, Yang W, Hsu WC. An LLVM-based hybrid binary translation system. In: Proc. of the 7th IEEE Int’l Symp. on
Industrial Embedded Systems (SIES 2012). Karlsruhe: IEEE, 2012. 229–236. [doi: 10.1109/SIES.2012.6356589]
[135] Wu J, Dong J, Fang RL, Zhao ZY, Gong XL, Wang WW, Zuo DC. Effective exploitation of SIMD resources in cross-ISA virtualization.
In: Proc. of the 17th ACM SIGPLAN/SIGOPS In’l Conf. on Virtual Execution Environments. Association for Computing Machinery,
2021. 84–97. [doi: 10.1145/3453933.3454016]
[136] Zhao C, Wu YF, Steffan JG, Amza C. Lengthening traces to improve opportunities for dynamic optimization. In: Proc. of the 12th
Workshop on Interaction Between Compilers and Computer Architectures (INTERACT 2008). Salt Lake City, 2008.
®
®
[137] Luk CK, Muth R, Patil H, Cohn R, Lowney G. Ispike: A post-link optimizer for the Intel Itanium architecture. In: Proc. of the 2004
Int’l Symp. on Code Generation and Optimization. San Jose: IEEE, 2004. 15–26. [doi: 10.1109/CGO.2004.1281660]
[138] D’antras A, Gorgovan C, Garside J, Luján M. Optimizing indirect branches in dynamic binary translators. ACM Trans. on Architecture
and Code Optimization, 2016, 13(1): 7. [doi: 10.1145/2866573]
[139] Liu YP, Hong DY, Wu JJ, Fu SY, Hsu WC. Exploiting asymmetric SIMD register configurations in ARM-to-x86 dynamic binary
translation. In: Proc. of the 26th Int’l Conf. on Parallel Architectures and Compilation Techniques (PACT). Portland: IEEE, 2017.
343–355. [doi: 10.1109/pact.2017.15]
[140] 2023, 12(14): 3025. [doi: 10.3390/electronics12143025]
Hong DY, Fu SY, Liu YP, Wu JJ, Hsu WC. Exploiting longer SIMD lanes in dynamic binary translation. In: Proc. of the 22nd Int’l
Conf. on Parallel and Distributed Systems (ICPADS). Wuhan: IEEE, 2016. 853–860. [doi: 10.1109/ICPADS.2016.0115]
[141] Hong DY, Liu YP, Fu SY, Wu JJ, Hsu WC. Improving SIMD parallelism via dynamic binary translation. ACM Trans. on Embedded
Computing Systems, 2018, 17(3): 61. [doi: 10.1145/3173456]
[142] Yi L, Shao YH, Yang GW, Wu JZ. Register allocation for QEMU dynamic binary translation systems. Int’l Journal of Hybrid
Information Technology, 2015, 8(2): 199–210. [doi: 10.14257/ijhit.2015.8.2.18]
[143] Wen YH, Tang DG, Qi FB. Register mapping and register function cutting out implementation in binary translation. Ruan Jian Xue
Bao/Journal of Software, 2009, 20: 1–7 (in Chinese with English abstract). http://www.jos.org.cn/1000-9825/09001.htm
[144] Yao Y, Lu ZY, Shi QS, Chen WZ. FPGA based hardware-software co-designed dynamic binary translation system. In: Proc. of the 23rd
Int’l Conf. on Field programmable Logic and Applications. Porto: IEEE, 2013. 1–4. [doi: 10.1109/FPL.2013.6645554]
[145] Lai JK, Yang W. Hyperchaining optimizations for an LLVM-based binary translator on x86-64 and RISC-V platforms. In: Proc. of the
50th Int’l Conf. on Parallel Processing Workshop. Lemont: Association for Computing Machinery, 2021. 13. [doi: 10.1145/3458744.
3473348]
[146] Sun LS, Wu YJ, Li LXY, Zhang CB, Tang JY. A dynamic and static binary translation method based on branch prediction. Electronics,

[147] Wang J, Pang JM, Liu XN, Yue F, Tan J, Fu LG. Dynamic translation optimization method based on static pre-translation. IEEE Access,
2019, 7: 21491–21501. [doi: 10.1109/ACCESS.2019.2897611]
[148] Ma RH, Guan HB, Zhu EZ, Yang HB, Yang YD, Liang AL. Partitioning the conventional DBT system for multiprocessors. Journal of
Computer Science and Technology, 2011, 26(3): 474–490. [doi: 10.1007/s11390-011-1148-1]
[149] Liu JK, Cao GJ, Zhang HG. Research on pipeline-based dynamic binary translation. In: Proc. of the 3rd Int’l Conf. on Computer Science
and Network Technology. Dalian: IEEE, 2013. 601–604. [doi: 10.1109/ICCSNT.2013.6967185]