Page 144 - 《软件学报》2024年第6期
P. 144

2720                                                       软件学报  2024  年第  35  卷第  6  期


                 [150]  Tu XP, Jin H, Yu ZB, Chen J, Hu YB. MT-BTRIMER: A master-slave multi-threaded dynamic binary translator. In: Proc. of the 5th Int’l
                      Conf. on Frontier of Computer Science and Technology. Changchun: IEEE, 2010. 51–56. [doi: 10.1109/FCST.2010.72]
                 [151]  Wescott B. The Every Computer Performance Book, Chapter 3: Useful Laws. CreateSpace Independent Publishing Platform, 2013.
                 [152]  Hong DY, Wu JJ, Liu YP, Fu SY, Hsu WC. Processor-tracing guided region formation in dynamic binary translation. ACM Trans. on
                      Architecture and Code Optimization, 2018, 15(4): 52. [doi: 10.1145/3281664]
                 [153]  Huang JS, Yang W, You YP. Profile-guided optimisation for indirect branches in a binary translator. Connection Science, 2022, 34(1):
                      749–765. [doi: 10.1080/09540091.2022.2041555]
                 [154]  Hong DY, Wu JJ, Yew PC, Hsu WC, Hsu CC, Liu PF, Wang CM, Chung YC. Efficient and retargetable dynamic binary translation on
                      multicores. IEEE Trans. on Parallel and Distributed Systems, 2014, 25(3): 622–632. [doi: 10.1109/tpds.2013.56]
                 [155]  Chen W, Wang ZY, Dou Q, Wang YW. A novel chaining approach to indirect control transfer instructions. In: Proc. of the 2011 IFIP
                      WG  8.4/8.9  Int’l  Cross  Domain  Conf.  and  Workshop  on  Availability,  Reliability  and  Security  for  Business,  Enterprise  and  Health
                      Information Systems. Vienna: Springer, 2011. 309–320. [doi: 10.1007/978-3-642-23300-5_24]
                 [156]  Kinder J, Zuleger F, Veith H. An abstract interpretation-based framework for control flow reconstruction from binaries. In: Proc. of the
                      10th Int’l Conf. on Verification, Model Checking, and Abstract Interpretation. Savannah: Springer, 2009. 214–228. [doi: 10.1007/978-3-
                      540-93900-9_19]
                      and Computing. Osaka: IEEE, 2011. 87–94. [doi: 10.1109/ICNC.2011.21]
                 [157]  Wang  J,  Pang  JM,  Fu  LG,  Yue  F,  Zhang  JH.  An  efficient  feedback  static  binary  translator  for  solving  indirect  branch.  Journal  of
                      Computer  Research  and  Development,  2019,  56(4):  742–754  (in  Chinese  with  English  abstract).  [doi:  10.7544/issn1000-1239.2019.
                      20170412]
                 [158]  Di Federico A, Agosta G. A jump-target identification method for multi-architecture static binary translation. In: Proc. of the 2016 Int’l
                      Conf. on Compilers, Architectures and Synthesis for Embedded Systems (CASES). Pittsburgh: ACM, 2016. 17. [doi: 10.1145/2968455.
                      2968514]
                 [159]  Wang WW, Yew PC, Zhai A, McCamant S, Wu YF, Bobba J. Enabling cross-ISA offloading for COTS binaries. In: Proc. of the 15th
                      Annual  Int’l  Conf.  on  Mobile  Systems,  Applications,  and  Services.  Niagara  Falls:  Association  for  Computing  Machinery,  2017.
                      319–331. [doi: 10.1145/3081333.3081337]
                 [160]  Wang WW, Yew PC, Zhai A, McCamant S. A general persistent code caching framework for dynamic binary translation (DBT). In:
                      Proc. of the 2016 USENIX Conf. on USENIX Annual Technical Conf. Denver: USENIX Association, 2016. 591–603.
                 [161]  Ibrahim AH, Abdelhalim MB, Hussein H, Fahmy A. Analysis of x86 instruction set usage for Windows 7 applications. In: Proc. of the
                      2nd Int’l Conf. on Computer Technology and Development. Cairo: IEEE, 2010. 511–516. [doi: 10.1109/ICCTD.2010.5645851]
                 [162]  Wang J, Pang JM, Fu LG, Yue F, Shan Z, Zhang JH. A dynamic and static combined register mapping method in binary translation.
                      Journal of Computer Research and Development, 2019, 56(4): 708–718 (in Chinese with English abstract). [doi: 10.7544/issn1000-1239.
                      2019.20170905]
                 [163]  Wang J, Pang JM, Fu LG, Shan Z, Yue F, Zhang JH. A binary translation backend registers allocation algorithm based on priority. In:
                      Proc. of the 5th Int’l Conf. on Geo-spatial Knowledge and Intelligence. Chiang Mai: Springer, 2017. 414–425. [doi: 10.1007/978-981-13-
                      0896-3_41]
                 [164]  Faravelon A, Gruber O, Pétrot F. Removing load/store helpers in dynamic binary translation. In: Andrade L, Rousseau F, eds. Multi-
                      processor System-on-chip 1: Architectures. Wiley, 2021. 133–160. [doi: 10.1002/9781119818298.ch7]
                 [165]  Wu J, Dong J, Fang RL, Zhang W, Wang WW, Zuo DC. WDBT: Wear characterization, reduction, and leveling of DBT systems for non-
                      volatile memory. In: Proc. of the 2021 Int’l Symp. on Memory Systems. Washington: Association for Computing Machinery, 2021. 15.
                      [doi: 10.1145/3488423.3519337]
                 [166]  Hallou N, Rohou E, Clauss P, Ketterlin A. Dynamic re-vectorization of binary code. In: Proc. of the 2015 Int’l Conf. on Embedded
                      Computer Systems: Architectures, Modeling, and Simulation (SAMOS). Samos: IEEE, 2015. 228–237. [doi: 10.1109/SAMOS.2015.
                      7363680]
                 [167]  Nakamura T, Miki S, Oikawa S. Automatic vectorization by runtime binary translation. In: Proc. of the 2nd Int’l Conf. on Networking


                 [168]  Lin CM, Fu SY, Hong DY, Liu YP, Wu JJ, Hsu WC. Exploiting vector processing in dynamic binary translation. In: Proc. of the 48th
                      Int’l Conf. on Parallel Processing (ICPP). Kyoto: ACM, 2019. 93. [doi: 10.1145/3337821.3337844]
                 [169]  Zhou RY, Wort G, Erdős M, Jones TM. The janus triad: Exploiting parallelism through dynamic binary modification. In: Proc. of the
                      15th  ACM  SIGPLAN/SIGOPS  Int’l  Conf.  on  Virtual  Execution  Environments.  Providence:  Association  for  Computing  Machinery,
                      2019. 88–100. [doi: 10.1145/3313808.3313812]
                 [170]  Jingu K, Shigenobu K, Ootsu K, Ohkawa T, Yokota T. Directive-based parallelization of for-loops at LLVM IR level. In: Proc. of the
   139   140   141   142   143   144   145   146   147   148   149