Page 140 - 《软件学报》2024年第6期
P. 140

2716                                                       软件学报  2024  年第  35  卷第  6  期


                      24(1): 68–79. [doi: 10.1145/233008.233025]
                 [63]  Chapman M, Magenheimer DJ, Ranganathan P. MagiXen: Combining binary translation and virtualization. Technical Report, HPL-
                      2007-77, Palo Alto: Enterprise Systems and Software Laboratory, 2007.
                 [64]  Bungale PP, Luk CK. PinOS: A programmable framework for whole-system dynamic instrumentation. In: Proc. of the 3rd Int’l Conf. on
                      Virtual Execution Environments. San Diego: Association for Computing Machinery, 2007. 137–147. [doi: 10.1145/1254810.1254830]
                 [65]  Sokolov RA, Ermolovich AV. Background optimization in full system binary translation. Programming and Computer Software, 2012,
                      38(3): 119–126. [doi: 10.1134/S0361768812030073]
                 [66]  Rokicki S, Rohou E, Derrien S. Hybrid-DBT: Hardware/software dynamic binary translation targeting VLIW. IEEE Trans. on Computer-
                      aided Design of Integrated Circuits and Systems, 2019, 38(10): 1872–1885. [doi: 10.1109/TCAD.2018.2864288]
                 [67]  Riedel S, Schuiki F, Scheffler P, Zaruba F, Benini L. Banshee: A fast LLVM-based RISC-V binary translator. In: Proc. of the 2021
                      IEEE/ACM Int’l Conf. On Computer Aided Design (ICCAD). Munich: IEEE, 2021. 1–9. [doi: 10.1109/ICCAD51958.2021.9643546]
                 [68]  Fu SY, Wu JJ, Hsu WC. Improving SIMD code generation in QEMU. In: Proc. of the 2015 Design, Automation & Test in Europe Conf.
                      & Exhibition (DATE). Grenoble: IEEE, 2015. 1233–1236.
                 [69]  Dullien T, Porst S. REIL: A platform-independent intermediate representation of disassembled code for static code analysis. In: Proc. of
                      the CanSecWest 2009. Vancouver, 2009.
                      and Implementation. San Diego: USENIX Association, 2008. 177–192.
                 [70]  Hex-Rays Sa. IDA-Pro: State-of-the-art binary code analysis tools. 2017. https://www.hex-rays.com/ida-pro/
                 [71]  Brumley D, Jager I, Avgerinos T, Schwartz EJ. BAP: A binary analysis platform. In: Proc. of the 23rd Int’l Conf. on Computer Aided
                      Verification. Snowbird: Springer, 2011. 463–469. [doi: 10.1007/978-3-642-22110-1_37]
                 [72]  Hasabnis  N,  Sekar  R.  Lifting  assembly  to  intermediate  representation:  A  novel  approach  leveraging  compilers.  ACM  SIGARCH
                      Computer Architecture, 2016, 44(2): 311–324. [doi: 10.1145/2980024.2872380]
                 [73]  Dong GX, Chen K, Zhu EZ, Zhang YC, Qi ZW, Guan HB. A translation framework for virtual execution environment on CPU/GPU
                      architecture.  In:  Proc.  of  the  3rd  Int’l  Symp.  on  Parallel  Architectures,  Algorithms  and  Programming.  IEEE,  2010.  130–137.
                      [doi: 10.1109/PAAP.2010.53]
                 [74]  Lattner C, Adve V. LLVM: A compilation framework for lifelong program analysis & transformation. In: Proc. of the 2004 Int’l Symp.
                      on Code Generation and Optimization. San Jose: IEEE, 2004. 75–86. [doi: 10.1109/CGO.2004.1281665]
                 [75]  Bits  L.  Framework  for  lifting  x86,  AMD64,  and  AArch64  program  binaries  to  LLVM  bitcode.  2022. https://github.com/liftingbits/
                      mcsema
                 [76]  Yadavalli SB, Smith A. Raising binaries to LLVM IR with Mctoll (WIP paper). In: Proc. of the 20th ACM SIGPLAN/SIGBED Int’l
                      Conf. on Languages, Compilers, and Tools for Embedded Systems. Phoenix: Association for Computing Machinery, 2019. 213–218.
                      [doi: 10.1145/3316482.3326354]
                 [77]  Chipounov V, Candea G. Dynamically translating x86 to LLVM using QEMU. 2010. http://infoscience.epfl.ch/record/149975/files/x86-
                      llvm-translator-chipounov_2.pdf
                 [78]  You YP, Lin TC, Yang W. Translating AArch64 floating-point instruction set to the x86-64 platform. In: Proc. of the 48th Int’l Conf. on
                      Parallel Processing. Kyoto: Association for Computing Machinery, 2019. 12. [doi: 10.1145/3339186.3339192]
                 [79]  Nethercote N. Dynamic binary analysis and instrumentation. Cambridge: University of Cambridge, 2004. [doi: 10.48456/tr-606]
                 [80]  Wang WW, McCamant S, Zhai A, Yew PC. Enhancing cross-ISA DBT through automatically learned translation rules. ACM SIGPLAN
                      Notices, 2018, 53(2): 84–97. [doi: 10.1145/3296957.3177160]
                 [81]  Song  CH,  Wang  WW,  Yew  PC,  Zhai  A,  Zhang  WH.  Unleashing  the  power  of  learning:  An  enhanced  learning-based  approach  for
                      dynamic binary translation. In: Proc. of the 2019 USENIX Conf. on USENIX Annual Technical Conf. Renton: USENIX Association,
                      2019. 77–89.
                 [82]  Bansal S, Aiken A. Binary translation using peephole superoptimizers. In: Proc. of the 8th USENIX Conf. on Operating Systems Design
                 [83]  Bansal  S,  Aiken  A.  Automatic  generation  of  peephole  superoptimizers.  ACM  SIGOPS  Operating  Systems  Review,  2006,  40(5):
                      394–403. [doi: 10.1145/1168917.1168906]
                 [84]  Jiang JH, Dong RC, Zhou ZJ, Song CH, Wang WW, Yew PC, Zhang WH. More with less—Deriving more translation rules with less
                      training data for DBTs using parameterization. In: Proc. of the 53rd Annual IEEE/ACM Int’l Symp. on Microarchitecture (MICRO).
                      Athens: IEEE, 2020. 415–426. [doi: 10.1109/MICRO50266.2020.00043]
                 [85]  Xu HR, Kjolstad F. Copy-and-Patch compilation: A fast compilation algorithm for high-level languages and bytecode. Proc. of the ACM
                      on Programming Languages, 2021, 5(OOPSLA): 136. [doi: 10.1145/3485513]
                 [86]  Li  CQ,  Liu  ZW,  Shang  YH,  He  LN,  Yan  XL.  A  hardware  non-invasive  mapping  method  for  condition  bits  in  binary  translation.
   135   136   137   138   139   140   141   142   143   144   145