Page 358 - 《软件学报》2021年第12期

4022 Journal of Software 软件学报 Vol.32, No.12, December 2021

[98] Kurth A, Riedel S, Zaruba F, et al. ATUNs: Modular and scalable support for atomic operations in a shared memory multiprocessor.
In: Proc. of the 57th ACM/IEEE Design Automation Conf. (DAC). 2020. 1−6. [doi: 10.1109/DAC18072. 2020.9218661]
[99] Pulte C, Pichon-Pharabod J, Kang J, et al. Promising-ARM/RISC-V: A simpler and faster operational concurrency model. In: Proc.
of the 40th ACM SIGPLAN Conf. on Programming Language Design and Implementation. New York: Association for Computing
Machinery. 2019. 1−15. [doi: 10.1145/3314221.3314624]
[100] Enokido T, Barolli L, Takizawa M. Network-Based Information Systems. Springer, 2007. [doi: 10.1007/978-3-540-74573-0]
[101] Glaser F, Tagliavini G, Rossi D, et al. Energy-efficient hardware-accelerated synchronization for shared-L1-memory
multiprocessor clusters. IEEE Trans. on Parallel and Distributed Systems. 2021,32(3):633-648. [doi: 10.1109/TPDS.2020.
3028691]
[102] Shi RB, Liu JJ, So HKH, et al. E-LSTM: Efficient inference of sparse LSTM on embedded heterogeneous system. In: Proc. of the
56th Annual Design Automation Conf. New York: Association for Computing Machinery, 2019. 1−6. [doi: 10.1145/3316781.
3317813]
[103] Armstrong A, Bauereiss T, Campbell B, et al. ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS. In: Proc. of the 8th Int’l
Workshop on Hardware and Architectural Support for Security and Privacy. New York: Association for Computing Machinery,
2019. 1−31. [doi: 10.1145/3290384]
[104] Deng SW, Gümusoglu D, Xiong WJ, et al. SecChisel framework for security verification of secure processor architectures. In: Proc.
of the 8th Int’l Workshop on Hardware and Architectural Support for Security and Privacy. New York: Association for Computing
Machinery, 2019. 1−8. [doi: 10.1145/3337167.3337174]
[105] Nelson L, Bornholt J, Gu RH, et al. Scaling symbolic evaluation for automated verification of systems code with Serval. In: Proc.
of the 27th ACM Symp. on Operating Systems Principles. New York: Association for Computing Machinery, 2019. 225−242. [doi:
10.1145/3341301.3359641]
[106] Khamis M, El-Ashry S, Shalaby A, et al. A configurable RISC-V for NoC-based MPSoCs: A framework for hardware emulation. In:
Proc. of the 11th Int’l Workshop on Network on Chip Architectures (NoCArc). 2018. 1−6. [doi: 10. 1109/NOCARC.2018.8541158]
[107] Dessouky G, Gens D, Haney P, et al. HardFails: Insights into software-exploitable hardware bugs. In: Proc. of the 28th USENIX
Conf. on Security Symposium. USENIX Association, 2019. 213−230. https://dl.acm.org/doi/abs/10.5555/3361338.3361354
[108] Nelson L, Geffen JV, Torlak E, et al. Specification and verification in the field: Applying formal methods to BPF just-in-time
compilers in the Linux kernel. In: Proc. of the 14th USENIX Symp. on Operating Systems Design and Implementation. USENIX
Association, 2020. 41−61. https://www.usenix.org/conference/osdi20/presentation/nelson
[109] Yu ZH, Huang B, Ma JY, et al. Labeled RISC-V: A new perspective on software-defined architecture. In: Proc. of the 1st
Workshop on Computer Architecture Research with RISC-V (CARRV 2017) Co-located with MICRO. 2017.
[110] Yu ZH, Liu ZG, Li YW, et al. Practice of chip agile development: Labeled RISC-V. Journal of Computer Research and
Development, 2019,56(1):35−48 (in Chinese with English abstract). [doi: 10.7544/issn1000-1239.2019. 20180771]
[111] Schuiki F, Zaruba F, Hoefler T, et al. Stream semantic registers: A lightweight RISC-V ISA extension achieving full compute
utilization in single-issue cores. IEEE Trans. on Computers, 2021,70(2):212−227. [doi: 10.1109/TC.2020.2987314]
[112] Dogan H, Ahmad M, Kahne B, et al. Accelerating synchronization using moving compute to data model at 1,000-core multicore
scale. ACM Trans. on Architecture and Code Optimization, 2019,16(1):1−27. [doi: 10.1145/3300208]
[113] Leidel JD, Wang X, Conlon F, et al. xBGAS: Toward a RISC-V ISA extension for global, scalable shared memory. In: Proc. of the
Workshop on Memory Centric High Performance Computing. New York: Association for Computing Machinery, 2018. 22−26. [doi:
10.1145/3286475.3286478]
[114] Williams B, Wang X, Leidel JD, et al. Collective communication for the RISC-V xBGAS ISA extension. In: Proc. of the 48th Int’l
Conf. on Parallel Processing: Workshops. 2019. 1−10. [doi: 10.1145/3339186.3339196]
[115] Wang X, Williams B, Leidel JD, et al. Remote atomic extension (RAE) for scalable high performance computing. In: Proc. of the
57th ACM/IEEE Design Automation Conf. (DAC). 2020. 1−6. [doi: 10.1109/DAC18072.2020.9218589]
[116] Morais L, Alvarez C, Bosch J, et al. Adding tightly-integrated task scheduling Acceleration to a RISC-V multi-core processor. In:
Proc. of the 52nd Annual IEEE/ACM Int’l Symp. on Microarchitecture. 2019. 861−872. [doi: 10. 1145/3352460.3358271]
[117] Zhou Y, Ren HX, Zhang YQ, et al. PRIMAL: Power inference using machine learning. In: Proc. of the 56th ACM/IEEE Design
Automation Conf. (DAC). 2019. 1−6. https://ieeexplore.ieee.org/document/8806775
[118] Bambini G, Balas R, Conficoni C, et al. An open-source scalable thermal and power controller for HPC processors. Proc. of the
38th IEEE Int’l Conf. on Computer Design (ICCD). 2020. 364−367.