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软件学报 ISSN 1000-9825, CODEN RUXUEW E-mail: jos@iscas.ac.cn
2025,36(5):2362−2380 [doi: 10.13328/j.cnki.jos.007192] [CSTR: 32375.14.jos.007192] http://www.jos.org.cn
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SPARC 架构下低时延微内核进程间通信设计

苏浩然, 李文泰, 古金宇, 臧斌宇, 陈海波, 管海兵

(上海交通大学 软件学院, 上海 200240)
通信作者: 古金宇, E-mail: gujinyu@sjtu.edu.cn

摘 要: 微内核系统将系统服务迁移到用户态运行, 因其架构隔离性而具有高可靠性的优势, 这一优势与航天领域
的需求相契合. SPARC 架构的处理器被广泛应用于航天飞船、卫星载荷以及星球车的控制设备上, 而该架构的寄
存器窗口机制会影响微内核进程间通信 (inter-process communication, IPC) 的性能, 其核间中断 (inter-processor
interrupt, IPI) 也会严重影响跨核 IPC 的效率. IPC 作为微内核系统的关键机制, 对微内核上应用程序的整体性能十
分重要. 基于对 SPARC 寄存器窗口机制的观察, 重新设计实现寄存器组机制, 由系统内核对寄存器窗口进行分配
和管理, 并藉此实现 SPARC 架构上的 BankedIPC. 同时, 在多核场景下, 针对 SPARC 上 IPI 性能较差的问题, 设计
实现 FlexIPC 以优化跨核 IPC 的性能. 使用这些方法对自研微内核 ChCore 上已经实现的通用的同步 IPC 进行优
化. 测试表明, 优化后 SPARC 上微内核的 IPC 平均性能提升至原来的 2 倍, 应用性能提升最高可达 15%.
关键词: 进程间通信; 微内核; SPARC 架构; 性能调优
中图法分类号: TP316

中文引用格式: 苏浩然, 李文泰, 古金宇, 臧斌宇, 陈海波, 管海兵. SPARC架构下低时延微内核进程间通信设计. 软件学报, 2025,
36(5): 2362–2380. http://www.jos.org.cn/1000-9825/7192.htm
英文引用格式: Su HR, Li WT, Gu JY, Zang BY, Chen HB, Guan HB. Low-latency Microkernel IPC Design for SPARC Architecture.
Ruan Jian Xue Bao/Journal of Software, 2025, 36(5): 2362–2380 (in Chinese). http://www.jos.org.cn/1000-9825/7192.htm

Low-latency Microkernel IPC Design for SPARC Architecture
SU Hao-Ran, LI Wen-Tai, GU Jin-Yu, ZANG Bin-Yu, CHEN Hai-Bo, GUAN Hai-Bing
(School of Software, Shanghai Jiao Tong University, Shanghai 200240, China)
Abstract: Microkernels migrate system services to user mode. Thanks to the isolated framework, microkernels are superior in high
reliability, which meets the needs of the aerospace field. SPARC processors are widely applied on the control equipment of spacecraft,
satellite payloads, and planetary vehicles. The register window mechanism of SPARC will affect the performance of inter-process
communication (IPC) on microkernels. Besides, its inter-processor interrupt (IPI) also seriously affects the efficiency of cross-core IPC. As
a key mechanism, IPC is vital to the overall performance of applications on microkernels. Through observing the register window
mechanism, this study redesigns and implements the register bank mechanism, where the register window is allocated and managed by the
kernel. Thus BankedIPC on SPARC is implemented. At the same time, as IPI underperforms on SPARC, FlexIPC is designed to optimize
the performance of cross-core IPC. These approaches are employed to optimize the general synchronous IPC implemented on a self-
developed microkernel ChCore. According to the test, the average IPC performance of microkernels on the optimized SPARC is about two
times better with the application performance up to 15%.
Key words: inter-process communication (IPC); microkernel; SPARC; performance optimization

在传统的宏内核架构下, 与操作系统功能相关的所有实现都被统一放置在内核特权级下运行, 因此宏内核架
构常常会带来可靠性和安全性问题, 比如当内核中的一个模块发生错误或者遭到攻击时, 就可能导致整个系统崩

* 基金项目: 国家自然科学基金青年基金 (62202292); 上海市科技创新行动计划 (22511101102)
收稿时间: 2023-04-03; 修改时间: 2024-01-18; 采用时间: 2024-03-28; jos 在线出版时间: 2024-06-14
CNKI 网络首发时间: 2024-06-17