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                      networks in hardware. arXiv:1705.06963, 2017.
                 [231]  Alippi C. Selecting accurate, robust, and minimal feedforward neural networks. IEEE Trans. on Circuits and Systems I: Fundamental
                      Theory and Applications, 2002, 49(12): 1799–1810. [doi: 10.1109/TCSI.2002.805710]
                 [232]  Nelson VP. Fault-tolerant computing: Fundamental concepts. Computer, 1990, 23(7): 19–25. [doi: 10.1109/2.56849]
                 [233]  Vatajelu EI, Prinetto P, Taouil M, Hamdioui S. Challenges and solutions in emerging memory testing. IEEE Trans. on Emerging Topics
                      in Computing, 2019, 7(3): 493–506. [doi: 10.1109/TETC.2017.2691263]
                 [234]  Xia LX, Gu P, Li BX, Tang TQ, Yin XL, Huangfu WQ, Yu SM, Cao Y, Wang Y, Yang HZ. Technological exploration of RRAM
                      crossbar array for matrix-vector multiplication. Journal of Computer Science and Technology, 2016, 31(1): 3–19. [doi: 10.1007/s11390-
                      016-1608-8]
                 [235]  Pop  P,  Izosimov  V,  Eles  P,  Peng  ZB.  Design  optimization  of  time-  and  cost-constrained  fault-tolerant  embedded  systems  with
                      checkpointing and replication. IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 2009, 17(3): 389–402. [doi: 10.1109/
                      TVLSI.2008.2003166]
                 [236]  Neti C, Schneider MH, Young ED. Maximally fault tolerant neural networks. IEEE Trans. on Neural Networks, 1992, 3(1): 14–23. [doi:
                      10.1109/72.105414]
                 [237]  Protzel  PW,  Palumbo  DL,  Arras  MK.  Performance  and  fault-tolerance  of  neural  networks  for  optimization.  IEEE  Trans.  on  Neural
                      Proc. of the 59th ACM/IEEE Design Automation Conf. San Francisco: ACM, 2022. 151–156. [doi: 10.1145/3489517.3530657]
                      Networks, 1993, 4(4): 600–614. [doi: 10.1109/72.238315]
                 [238]  Indiveri G. A low-power adaptive integrate-and-fire neuron circuit. In: Proc. of the 2003 Int’l Symp. on Circuits and Systems. Bangkok:
                      IEEE, 2003. IV-820–VI-823. [doi: 10.1109/ISCAS.2003.1206342]
                 [239]  Spyrou T, El-Sayed SA, Afacan E, Camuñas-Mesa LA, Linares-Barranco B, Stratigopoulos HG. Reliability analysis of a spiking neural
                      network hardware accelerator. In: Proc. of the 2022 Design, Automation & Test in Europe Conf. & Exhibition (DATE). Antwerp: IEEE,
                      2022. 370–375. [doi: 10.23919/DATE54114.2022.9774711]
                 [240]  Vatajelu EI, Di Natale G, Anghel L. Special session: Reliability of hardware-implemented spiking neural networks (SNN). In: Proc. of
                      the 37th IEEE VLSI Test Symp. (VTS). Monterey: IEEE, 2019. 1–8. [doi: 10.1109/VTS.2019.8758653]
                 [241]  Goodman D, Brette R. Brian: A simulator for spiking neural networks in Python. Frontiers in Neuroinformatics, 2008, 2: 5. [doi: 10.
                      3389/neuro.11.005.2008]
                 [242]  Schuman CD, Mitchell JP, Johnston JT, Parsa M, Kay B, Date P, Patton RM. Resilience and robustness of spiking neural networks for
                      neuromorphic systems. In: Proc. of the 2020 Int’l Joint Conf. on Neural Networks (IJCNN). Glasgow: IEEE, 2020. 1–10. [doi: 10.1109/
                      IJCNN48605.2020.9207560]
                 [243]  Spyrou  T,  El-Sayed  SA,  Afacan  E,  Camuñas-Mesa  LA,  Linares-Barranco  B,  Stratigopoulos  HG.  Neuron  fault  tolerance  in  spiking
                      neural  networks.  In:  Proc.  of  the  2021  Design,  Automation  &  Test  in  Europe  Conf.  &  Exhibition  (DATE).  Grenoble:  IEEE,  2021.
                      743–748. [doi: 10.23919/DATE51398.2021.9474081]
                 [244]  Srivastava  N,  Hinton  G,  Krizhevsky  A,  Sutskever  I,  Salakhutdinov  R.  Dropout:  A  simple  way  to  prevent  neural  networks  from
                      overfitting. The Journal of Machine Learning Research, 2014, 15(1): 1929–1958.
                 [245]  Chen QY, He GQ, Wang XY, Xu J, Shen SR, Chen H, Fu YX, Li L. A 67.5 μJ/prediction accelerator for spiking neural networks in
                      image  segmentation.  IEEE  Trans.  on  Circuits  and  Systems  II:  Express  Briefs,  2022,  69(2):  574–578.  [doi:  10.1109/TCSII.2021.
                      3098633]
                 [246]  Zhang JL, Liang MX, Wei JS, Wei SJ, Chen H. A 28 nm configurable asynchronous SNN accelerator with energy-efficient learning. In:
                      Proc.  of  the  27th  IEEE  Int’l  Symp.  on  Asynchronous  Circuits  and  Systems  (ASYNC).  Beijing:  IEEE,  2021.  34–39.  [doi:  10.1109/
                      ASYNC48570.2021.00013]
                 [247]  Putra RVW, Hanif MA, Shafique M. SoftSNN: Low-cost fault tolerance for spiking neural network accelerators under soft errors. In:


                 [248]  Yerima WY, Ikechukwu OM, Dang KN, Abdallah AB. Fault-tolerant spiking neural network mapping algorithm and architecture to 3D-
                      NoC-based neuromorphic systems. IEEE Access, 2023, 11: 52429–52443. [doi: 10.1109/ACCESS.2023.3278802]
                 [249]  Liu JX, Harkin J, Maguire LP, Mcdaid LJ, Wade JJ. SPANNER: A self-repairing spiking neural network hardware architecture. IEEE
                      Trans. on Neural Networks and Learning Systems, 2018, 29(4): 1287–1300. [doi: 10.1109/TNNLS.2017.2673021]
                 [250]  Johnson AP, Liu JX, Millard AG, Karim S, Tyrrell AM, Harkin J, Timmis J, McDaid L, Halliday DM. Time-multiplexed system-on-
                      chip using fault-tolerant astrocyte-neuron networks. In: Proc. of the 2018 IEEE Symp. Series on Computational Intelligence (SSCI).
                      Bangalore: IEEE, 2018. 1076–1083. [doi: 10.1109/SSCI.2018.8628710]
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