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韩金池 等: Spike-FlexiCAS: 支持缓存架构灵活配置的 RISC-V 处理器模拟器                                3969


                     of the ACM Asia Conf. on Computer and Communications Security. Melbourne: ACM, 2023. 163–176. [doi: 10.1145/3579856.3595794]
                 [28]   Werner  M,  Unterluggauer  T,  Giner  L,  Schwarz  M,  Gruss  D,  Mangar  S.  ScatterCache:  Thwarting  cache  attacks  via  cache  set
                     randomization. In: Proc. of the 28th USENIX Security Symp. Santa Clara: USENIX Association, 2019. 675–692.
                 [29]   Intel. coffee_lake. 2017. https://en.wikichip.org/wiki/intel/microarchitectures/coffee_lake
                 [30]   Asanović K, Avizienis R, Bachrach J, Beamer S, Biancolin D, Celio C, Cook H, Dabbelt D, Hauser J, Izraelevitz A, Karandikar S, Keller
                     B, Kim D, Koenig J. The rocket chip generator. Berkeley: University of California, 2016.
                 [31]   Amid A, Biancolin D, Gonzalez A, Grubb D, Karandikar S, Liew H, Magyar A, Mao H, Ou A, Pemberton N, Rigge P, Schmidt C, Wright
                     J, Zhao J, Shao YS, Asanovic K, Nikolic B. Chipyard: Integrated design, simulation, and implementation framework for custom SoCs.
                     IEEE Micro, 2020, 40(4): 10–21. [doi: 10.1109/MM.2020.2996616]
                 [32]   Cook H. Productive design of extensible on-chip memory hierarchies [Ph.D. Thesis]. Berkeley: University of California, 2016.
                 [33]   Jaleel A, Theobald KB, Steely SC Jr, Emer J. High performance cache replacement using re-reference interval prediction (RRIP). In:
                     Proc. of the 37th Int’l Symp. on Computer Architecture. Saint-Malo: ACM, 2010. 60–71. [doi: 10.1145/1815961.1815971]
                 [34]   Tatar A, Trujillo D, Giuffrida C, Bos H. TLB;DR: Enhancing TLB-based attacks with TLB desynchronized reverse engineering. In: Proc.
                     of the 31st USENIX Security Symp. Boston: USENIX Association, 2022. 989–1007.
                 [35]   Alglave  J,  Maranget  L,  Sarkar  S,  Sewell  P.  Litmus:  Running  tests  against  hardware.  In:  Proc.  of  the  17th  Int’l  Conf.  on  Tools  and
                     Algorithms for the Construction and Analysis of Systems. Saarbrücken: Springer, 2011. 41–44. [doi: 10.1007/978-3-642-19835-9_5]
                 [36]   Jagtap R, Diestelhorst S, Hansson A, Jung M, Wehn N. Exploring system performance using elastic traces: Fast, accurate and portable. In:
                     Proc.  of  the  2016  Int’l  Conf.  on  Embedded  Computer  Systems:  Architectures,  Modeling  and  Simulation.  Agios  Konstantinos:  IEEE,
                     2016. 96–105. [doi: 10.1109/SAMOS.2016.7818336]
                 [37]   Sangaiah K, Lui M, Jagtap R, Diestelhorst S, Nilakantan S, More A, Taskin B, Hempstead M. SynchroTrace: Synchronization-aware
                     architecture-agnostic traces for lightweight multicore simulation of CMP and HPC workloads. ACM Trans. on Architecture and Code
                     Optimization, 2018, 15(1): 2. [doi: 10.1145/3158642]

                 附中文参考文献:
                 [9]   王崇, 魏帅, 张帆, 宋克. 缓存侧信道防御研究综述. 计算机研究与发展, 2021, 58(4): 794–810. [doi: 10.7544/issn1000-1239.2021.
                    20200500]


                             韩金池(2000-), 男, 硕士生, 主要研究领域为计                 马浩(1994-), 男, 博士生, 主要研究领域为随机
                            算机体系结构安全.                                    化缓存侧信道防御.





                             王智栋(2001-), 男, 硕士生, 主要研究领域为计                 宋威(1983-), 男, 副研究员, 博士生导师, CCF

                            算机体系结构安全.                                    高级会员, 主要研究领域为安全处理器设计, 计

                                                                         算机体系结构安全, 编译器的安全优化技术, 基

                                                                         于  RISC-V  的处理器设计.
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