Page 165 - 《软件学报》2020年第10期

张倩颖 等:抗电路板级物理攻击的操作系统防御技术研究 3141

[29] Rogers B, Chhabra S, Prvulovic M, Solihin Y. Using address independent seed encryption and bonsai merkle trees to make secure
processors OS- and performance-friendly. In: Proc. of the 40th Annual IEEE/ACM Int’l Symp. on Microarchitecture (MICRO).
IEEE, 2007. 183–196. [doi: 10.1109/MICRO.2007.16]
[30] Vaslin R, Gogniat G, Diguet JP, Tessier R, Burleson W. Low latency solution for confidentiality and integrity checking in
embedded systems with off-chip memory. In: Proc. of the 3rd Int'l Workshop on Reconfigurable Communication-centric Systems-
on-Chip (ReCoSoC). 2007. 146–153.
[31] Lee M, Ahn M, Kim EJ. I2SEMS: Interconnects-independent security enhanced shared memory multiprocessor systems. In: Proc.
of the 16th Int’l Conf. on Parallel Architecture and Compilation Techniques (PACT). IEEE, 2007. 94–103. [doi: 10.1109/PACT.
2007.4336203]
[32] Elbaz R, Champagne D, Lee RB, Torres L, Sassatelli G, Guillemin P. TEC-Tree: A low-cost, parallelizable tree for efficient
defense against memory replay attacks. In: Proc. of the 9th Int’l Workshop on Cryptographic Hardware and Embedded Systems
(CHES). 2007. 289–302. [doi: 10.1007/978-3-540-74735-2_20]
[33] Su LF, Courcambeck S, Guillemin P, Schwarz C, Pacalet R. SecBus: Operating system controlled hierarchical page-based memory
bus protection. In: Proc. of the 12th Design, Automation and Test in Europe. IEEE, 2009. 570–573. [doi: 10.1109/DATE.
2009.5090729]
[34] Enck W, Butler K, Richardson T, McDaniel P, Smith A. Defending against attacks on main memory persistence. In: Proc. of the
24th Annual Computer Security Applications Conf. (ACSAC). IEEE, 2008. 65–74. [doi: 10.1109/ACSAC.2008.45]
[35] Rogers B, Yan CY, Chhabra S, Prvulovic M, Solihin Y. Single-level integrity and confidentiality protection for distributed shared
memory multiprocessors. In: Proc. of the 14th Int’l Symp. on High Performance Computer Architecture (HPCA). IEEE, 2008.
161–172. [doi: 10.1109/HPCA.2008.4658636]
[36] Champagne D, Elbaz R, Lee RB. The reduced address space (RAS) for application memory authentication. In: Proc. of the 11th
Int’l Conf. on Information Security (ISC). Berlin, Heidelberg: Springer-Verlag, 2008. 47–63. [doi: 10.1007/978-3-540-85886-7_4]
[37] Vig S, Juneja R, Jiang GY, Lam SK, Ou CH. Framework for fast memory authentication using dynamically skewed integrity tree.
IEEE Trans. on Very Large Scale Integration (VLSI) Systems, 2019,27(10):2331–2343. [doi: 10.1109/TVLSI.2019.2923004]
[38] Chhabra S, Rogers B, Solihin Y, Prvulovic M. SecureME: A hardware-software approach to full system security. In: Proc. of the
25th Int’l Conf. on Supercomputing (ICS). ACM, 2011. 108–119. [doi: 10.1145/1995896.1995914]
[39] Chhabra S, Solihin Y. i-NVMM: A secure non-volatile main memory system with incremental encryption. In: Proc. of the 38th
Annual Int’l Symp. on Computer Architecture (ISCA). IEEE, 2011. 177–188. [doi: 10.1145/2000064.2000086]
[40] Elbaz R, Champagne D, Gebotys C, Lee RB, Potlapally N, Torres L. Hardware mechanisms for memory authentication: A survey
of existing techniques and engines. Trans. on Computational Science IV. Berlin, Heidelberg: Springer-Verlag, 2009. 1–22. [doi:
10.1007/978-3-642-01004-0_1]
[41] Henson M, Taylor S. Memory encryption: A survey of existing techniques. ACM Computing Surveys, 2014,46(4):53:1–53:26.
[doi: 10.1145/2566673]
[42] McKeen F, Alexandrovich I, Berenzon A, Rozas CV, Shafi H, Shanbhogue V, Savagaonkar UR. Innovative instructions and
software model for isolated execution. In: Proc. of the 2nd Int’l Workshop on Hardware and Architectural Support for Security
and Privacy (HASP). ACM, 2013. 10. [doi: 10.1145/2487726.2488368]
[43] Anati I, Gueron S, Johnson SP, Scarlata VR. Innovative technology for CPU based attestation and sealing. In: Proc. of the 2nd
Int’l Workshop on Hardware and Architectural Support for Security and Privacy (HASP). ACM, 2013. 13.
[44] Kaplan D, Powell J, Woller T. AMD memory encryption. White paper. Advanced Micro Devices, Inc., 2016.
[45] Lin JQ, Luo B, Guan L, Jing JW. Secure computing using registers and caches: The problem, challenges, and solutions. IEEE
Security & Privacy, 2016,14(6):63–70. [doi: 10.1109/MSP.2016.130]
[46] Huo WJ. Research and design of secure run-time mechanism for embedded processor [Ph.D. Thesis]. Wuhan: Huazhong
University of Science and Technology, 2010 (in Chinese with English abstract).
[47] GlobalPlatform Device Committee. TEE protection profile, version 1.2.1. 2016. https://globalplatform.org/specs-library/tee-
protection-profile-v1-2-1
[48] Gutmann P. Data remanence in semiconductor devices. In: Proc. of the 10th USENIX Security Symp. (USENIX Security).
USENIX Association, 2001. 39–54. [doi: 10.5555/1251327.1251331]