Page 110 - 《软件学报》2020年第10期
P. 110
3086 Journal of Software 软件学报 Vol.31, No.10, October 2020
[15] Conti F, Rossi D, Pullini A, et al. PULP: A ultra-low power parallel accelerator for energy-efficient and flexible embedded vision.
Journal of Signal Processing Systems, 2015,84(3):339–354. [doi: 10.1007/s11265-015-1070-9]
[16] Schiavone MG, Benini L. A near-threshold RISC-V core with DSP extensions for scalable IoT endpoint devices. IEEE Trans. on
Very Large Scale Integration Systems, 2017,25(10):2700–2713.
[17] Lou W, Wang C, Gong L, et al. RV-CNN: Flexible and efficient instruction set for CNNs based on RISC-V processors. In: Proc. of
the Int’l Symp. on Advanced Parallel Processing Technologies. Cham: Springer-Verlag, 2019. 3–14.
[18] Bao Y, Wang S. Labeled von Neumann architecture for software-defined cloud. Journal of Computer Science and Technology,
2017,32(2):219–223. [doi: 10.1007/s11390-017-1716-0]
[19] Cong J, Ghodrat MA, Gill M, et al. Accelerator-rich architectures: Opportunities and progresses. In: Proc. of the Design
Automation Conf. IEEE, 2014. 1–6. [doi: 10.1145/2593069.2596667]
[20] Lu LQ, Zheng SZ, Xiao QC, et al. Accelerating convolutional neural networks on FPGAs. Science in China (Information Sciences),
2019,49(3):277–294 (in Chinese with English abstract). [doi: 10.1360/N112018-00291]
[21] Alwani M, Chen H, Ferdman M, et al. Fused-layer CNN accelerators. In: Proc. of the 49th Annual IEEE/ACM Int’l Symp. on
Microarchitecture (MICRO) IEEE, 2016. 1–12. [doi: 10.1109/micro.2016.7783725]
[22] Gysel P, Pimentel J, Motamedi M, et al. Ristretto: A framework for empirical study of resource-efficient inference in convolutional
neural networks. IEEE Trans. on Neural Networks, 2018,29(11):5784–5789.
[23] Zhang C, Li P, Sun G, et al. Optimizing FPGA-based accelerator design for deep convolutional neural networks. In: Proc. of the
2015 ACM/SIGDA Int’l Symp. on Field-programmable Gate Arrays. ACM, 2015. 161–170.
[24] Suda N, Chandra V, Dasika G, et al. Throughput-optimized OpenCL-based FPGA accelerator for large-scale convolutional neural
networks. In: Proc. of the 2016 ACM/SIGDA Int’l Symp. on Field-programmable Gate Arrays. ACM, 2016. 16–25.
[25] Guan Y, Liang H, Xu N, et al. FP-DNN: An automated framework for mapping deep neural networks onto FPGAs with RTL-HLS
hybrid templates. In: Proc. of the 25th IEEE Annual Int’l Symp. on Field-programmable Custom Computing Machines (FCCM).
IEEE, 2017. 152–159.
附中文参考文献:
[20] 卢丽强,郑思泽,肖倾城,等.面向卷积神经网络的 FPGA 设计.中国科学(信息科学),2019,49(3):277−294. [doi: 10.1360/N112018-
00291]
娄文启(1995-),男,博士生,主要研究领域 宫磊(1990-),男,博士后,CCF 专业会员,
为神经网络处理器,可重构硬件加速器. 主要研究领域为计算机系统结构,可重构
硬件加速器,神经网络处理器.
王超(1985-),男,博士,副教授,CCF 高级 周学海(1966-),男,博士,教授,博士生导
会员,主要研究领域为神经网络加速器,深 师,CCF 高级会员,主要研究领域为计算机
度学习处理器. 体系结构,嵌入式系统.