Page 72 - 《软件学报》2026年第6期

刘佳玮 等: 面向 RISC-V 架构的深度学习算子测试 2391

Abstract: With the rapid development of edge computing and intelligent end-side software, the RISC-V architecture attracts increasing
attention in both academia and industry due to its open-source, modular, and low-cost characteristics. However, deploying intelligent
software on the RISC-V architecture presents significant challenges. The execution of intelligent software relies on deep learning operators,
such as convolution, matrix multiplication, and normalization. Once defects occur in these operators, the execution efficiency, accuracy,
and reliability of a large number of upper-layer intelligent applications are directly affected, making operator quality evaluation critically
important. Existing operator testing methods are primarily designed for x86 architectures and have difficulty characterizing the impact of
varying computational complexity on RISC-V platforms under constraints such as limited memory capacity, power consumption, and
system resources. To address this issue, this study proposes RIVdoo, a deep learning operator testing method tailored for the RISC-V
architecture. RIVdoo systematically covers different computational workloads through a grouping strategy based on operator input-space
complexity, evaluates accuracy, execution efficiency, memory usage, and system overhead using multidimensional metrics, and introduces a
differential testing mechanism with complexity amplification factors to effectively identify performance anomalies and architectural
adaptation issues. Experiments covering 47 operators across compute-intensive, memory-intensive, and lightweight categories demonstrate
that RIVdoo reveals significant performance trade-offs and adaptation differences among existing operator libraries and optimization
strategies on the RISC-V architecture. Specifically, TFLite trades 1.5×–2× memory overhead for 30%–50% performance improvement,
which leads to memory bottlenecks in resource-constrained scenarios; TVM’s dynamic storage scheduling incurs 60%–150% higher page
fault rates than TFLite due to the limited TLB and cache capacity of RISC-V; RVV vectorization causes performance degradation for
certain operators and low-complexity workloads because of software emulation and startup overhead, indicating that existing optimization
strategies lack targeted design for RISC-V platform characteristics. The results demonstrate that the runtime behavior of different operator
implementations and optimization strategies on the RIVdoo architecture exhibits strong complexity-dependent characteristics, and that
output correctness alone is insufficient to reflect real deployment performance. RISC-V provides a systematic evaluation methodology for
operator adaptability analysis and optimization on RISC-V platforms.
Key words: deep learning operator; differential testing; RISC-V; operator deployment

RISC-V 架构是一种基于精简指令集 (RISC) 思想的开源指令集架构, 随着 RISC-V 架构在边缘计算和物联网
领域的快速发展, 其模块化设计、可扩展性和成本优势正逐渐获得学术界与产业界的广泛关注 [1,2] . 特别是在资源
受限的嵌入式场景中, RISC-V 架构凭借低成本和灵活性, 为复杂软件的高效部署提供了新的可能性 [3] . 与此同时,
基于深度学习模型的复杂软件在视觉识别、语音处理和智能控制等领域的广泛应用 [4] , 使得在基于 RISC-V 架构
的平台上部署神经网络模型成为亟需解决的问题 [5,6] .
然而, 深度学习模型的执行高度依赖底层算子库的性能与稳定性, 算子是实现特定张量运算的基本功能单元,
例如卷积 (Conv2D)、矩阵乘法 (MatMul)、归一化 (BatchNorm) 等 [7,8] . 模型的执行过程是由大量算子按计算图依
次调用完成的, 因此算子的性能、精度与稳定性直接决定了整个模型在目标平台上的运行质量 [9,10] . 若算子实现存
在性能瓶颈或资源利用低效, 则即便模型结构先进, 也难以在硬件上获得预期效果. 当前主流算子库 (如 TVM、
TensorFlow lite (TFLite) 等) 主要面向 x86 与 ARM 架构进行优化, 对 RISC-V 架构的支持尚不完善, 其在算子层面
的执行性能、资源利用效率以及运行稳定性仍存在诸多未知因素. 因此, 针对 RISC-V 架构的算子测试与质量评
估成为构建可用深度学习生态的基础性问题.
与成熟的 x86 和 ARM 生态相比, RISC-V 架构上的算子部署面临若干独特挑战. 首先, RISC-V 架构在编译器
优化、运行时库支持以及硬件加速单元方面尚处于发展阶段, 可能导致算子实际性能与理论预期存在显著差距 [11] .
其次, RISC-V 架构通常运行在内存容量有限、功耗约束严格以及散热能力不足的环境中, 使得算子执行效率不仅
影响计算性能, 也直接关系到系统稳定性与寿命 [12,13] . 此外, RISC-V 架构上的部署多依赖静态交叉编译方式, 虽然
简化了依赖管理, 但增加了移植复杂度并可能引入新的性能损失 [14−16] .
这些 RISC-V 架构的独特挑战使得传统的深度学习算子测试方法暴露出两个关键局限性. 针对资源约束和热
管理挑战, 现有算子测试方法采用统一的参数配置策略, 无法区分不同运算复杂度对有限内存、功耗预算和散热
能力的差异化影响, 缺乏系统性的输入空间划分来识别复杂度相关的资源利用模式和热行为变化. 针对编译优化
不足和架构特性差异挑战, 现有算子测试方法主要围绕 x86 和 ARM 架构开展研究, 其测试指标主要关注通用性
能问题, 而对 RISC-V 架构特有的约束 (如精简指令集效率、静态编译代码膨胀、缓存层级限制等) 缺乏针对性评
估维度, 无法有效识别这些架构特有因素导致的算子质量问题.
针对上述问题, 本文提出一种面向 RISC-V 架构的深度学习算子质量评估方法 RIVdoo. 针对资源约束环境下