Page 69 - 《软件学报》2026年第6期

2388 软件学报 2026 年第 37 卷第 6 期

[25] Gerlach L, Weber D, Zhang RY, Schwarz M. A security RISC: Microarchitectural attacks on hardware RISC-V CPUs. In: Proc. of the
2023 IEEE Symp. on Security and Privacy (SP). San Francisco: IEEE, 2023. 2321–2338. [doi: 10.1109/SP46215.2023.10179399]
[26] Papadimitriou G, Gizopoulos D. Demystifying the system vulnerability stack: Transient fault effects across the layers. In: Proc. of the
48th ACM/IEEE Annual Int’l Symp. on Computer Architecture (ISCA). Valencia: IEEE, 2021. 902–915. [doi: 10.1109/ISCA52012.2021.
00075]
[27] Raia G, Rigano G, Vincenzoni D, Martina M. A case study on formal equivalence verification between a C/C++ model and its RTL
design. In: Proc. of the 26th Int’l Conf. on Formal Methods. Milan: Springer, 2025. 373–389. [doi: 10.1007/978-3-031-71177-0_23]
[28] Godbole A, Huffman B, Liu FF, Rozas CV, Seshia SA. PYCALIPER: Python-embedded infrastructure for RTL verification and
specification synthesis. In: Proc. of the 37th Int’l Conf. on Computer Aided Verification. Zagreb: Springer, 2025. 408–425. [doi: 10.1007/
978-3-031-98682-6_21]
[29] Rajendran SR, Mukherjee R, Chakraborty RS. SoK: Physical and logic testing techniques for hardware Trojan detection. In: Proc. of the
4th ACM Workshop on Attacks and Solutions in Hardware Security. ACM, 2020. 103–116. [doi: 10.1145/3411504.3421211]
[30] Li XP, Li XH, Dall C, Gu RH, Nieh J, Sait Y, Stockwell G. Design and verification of the ARM confidential compute architecture. In:
Proc. of the 16th USENIX Symp. on Operating Systems Design and Implementation. Carlsbad: USENIX Association, 2022. 465–484.
[31] Zhan BH, Wu ZL. Formal verification of circuit design. Science and Technology Foresight, 2023, 2(1): 23–32 (in Chinese with English
abstract). [doi: 10.3981/j.issn.2097-0781.2023.01.002]
[32] Orenes-Vera M, Manocha A, Wentzlaff D, Martonosi M. AutoSVA: Democratizing formal verification of RTL module interactions. In:
Proc. of the 58th ACM/IEEE Design Automation Conf. (DAC). San Francisco: IEEE, 2021. 535–540. [doi: 10.1109/DAC18074.2021.
9586118]
[33] Tan QH, Yang YH, Bourgeat T, Malik S, Yan MJ. RTL verification for secure speculation using contract shadow logic. In: Proc. of the
30th ACM Int’l Conf. on Architectural Support for Programming Languages and Operating Systems (Vol. 1). Rotterdam: ACM, 2025.
970–986. [doi: 10.1145/3669940.3707243]
[34] Trippel T, Shin KG, Chernyakhovsky A, Kelly G, Rizzo D, Hicks M. Fuzzing hardware like software. In: Proc. of the 31st USENIX
Security Symp. Boston: USENIX Association, 2022. 3237–3254.
[35] Ma RY, Huang JY, Zhang SJ, Xie Y, Luo GJ. NoCFuzzer: Automating NoC verification in UVM. IEEE Trans. on Computer-aided
Design of Integrated Circuits and Systems, 2025, 44(1): 371–384. [doi: 10.1109/TCAD.2024.3430195]
[36] Reis S, Abreu R, d’Amorim M, Fortunato D. Leveraging practitioners’ feedback to improve a security linter. In: Proc. of the 37th
IEEE/ACM Int’l Conf. on Automated Software Engineering. Rochester: ACM, 2023. 66. [doi: 10.1145/3551349.3560419]
[37] CHIPS Alliance. Verible. 2020. https://github.com/chipsalliance/verible
[38] Synopsys. SpyGlass Lint: Early design analysis. 2018. https://www.synopsys.com/verification/static-and-formal-verification/spyglass/
spyglass-lint.html
[39] Ryou Y, Joh S, Yang J, Kim S, Kim Y. Code understanding linter to detect variable misuse. In: Proc. of the 37th IEEE/ACM Int’l Conf.
on Automated Software Engineering. Rochester: ACM, 2023. 133. [doi: 10.1145/3551349.3559497]
[40] Cui X, Wu JZ, Ling X, Luo TY, Yang MT, Ou WX. Exploring large language models for analyzing open source license conflicts: How
far are we? In: Proc. of the 47th IEEE/ACM Int’l Conf. on Software Engineering Companion (ICSE-Companion). Ottawa: IEEE, 2025.
291–302. [doi: 10.1109/ICSE-Companion66252.2025.00083]
[41] Liu S, Fang WJ, Lu Y, Wang J, Zhang QJ, Zhang HC, Xie ZY. RTLCoder: Fully open-source and efficient LLM-assisted RTL code
generation technique. IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems, 2025, 44(4): 1448–1461. [doi: 10.1109/
TCAD.2024.3483089]
[42] Wang X, Wan GW, Wong SZ, Zhang L, Liu TY, Tian Q, Ye JM. ChatCPU: An agile CPU design and verification platform with LLM.
In: Proc. of the 61st ACM/IEEE Design Automation Conf. (DAC). San Francisco: ACM, 2024. 212. [doi: 10.1145/3649329.3658493]
[43] Chen YX, Wu JZ, Ling X, Li CJ, Rui ZQ, Luo TY, Wu YJ. When large language models confront repository-level automatic program
repair: How well they done? In: Proc. of the 46th IEEE/ACM Int’l Conf. on Software Engineering: Companion. Lisbon: ACM, 2024.
459–471. [doi: 10.1145/3639478.3647633]
[44] Collini L, Ahmad B, Ah-kiow J, Karri R. MARVEL: Multi-agent RTL vulnerability extraction using large language models.
arXiv:2505.11963, 2025.
[45] Ahmad B, Ah-Kiow J, Tan B, Karri R, Pearce H. FLAG: Finding line anomalies (in RTL code) with generative AI. ACM Trans. on
Design Automation of Electronic Systems, 2025, 30(6): 103. [doi: 10.1145/3736411]
[46] Fan FH, Xia YJ, Kuang L. SecV: LLM-based secure Verilog generation with clue-guided exploration on hardware-CWE knowledge
graph. In: Proc. of the 34th Int’l Joint Conf. on Artificial Intelligence. Montreal: ijcai.org, 2025. 8049–8057. [doi: 10.24963/ijcai.2025/895]