Page 47 - 《软件学报》2026年第6期
P. 47

2366                                                       软件学报  2026  年第  37  卷第  6  期


                 [15]   Armstrong A, Bauereiss T, Campbell B, Reid A, Gray KE, Norton RM, Mundkur P, Wassell M, French J, Pulte C, Flur S, Stark I,
                     Krishnaswami N, Sewell P. ISA semantics for ARMv8-a, RISC-V, and CHERI-MIPS. Proc. of the ACM on Programming Languages,
                     2019, 3(POPL): 71. [doi: 10.1145/3290384]
                 [16]   Bora S, Paily R. A high-performance core micro-architecture based on RISC-V ISA for low power applications. IEEE Trans. on Circuits
                     and Systems II: Express Briefs, 2021, 68(6): 2132–2136. [doi: 10.1109/TCSII.2020.3043204]
                 [17]   Hassan QF, Sagahyroon A. RISC-V: A comprehensive overview of an emerging ISA for the AI-IoT era. In: Hassan QF, ed. Advances in
                     the Internet of Things. Boca Raton: CRC Press, 2025. 244–284.
                 [18]   Lazzeri E, Forlin BE, Furano G, Ottavi M, Cassano L. An experimental comparison of RISC-V processors: Performance, power, area and
                     security-special  session  paper.  In:  Proc.  of  the  2024  IEEE  Int’l  Symp.  on  Defect  and  Fault  Tolerance  in  VLSI  and  Nanotechnology
                     Systems (DFT). Didcot: IEEE, 2024. 1–6. [doi: 10.1109/DFT63277.2024.10753540]
                 [19]   Lattner C, Adve V. LLVM: A compilation framework for lifelong program analysis & transformation. In: Proc. of the 2004 Int’l Symp.
                     on Code Generation and Optimization (CGO 2004). San Jose: IEEE, 2004. 75–86. [doi: 10.1109/CGO.2004.1281665]
                 [20]   de la Torre JC, Ruiz P, Dorronsoro B, Galindo PL. Analyzing the influence of LLVM code optimization passes on software performance.
                     In:  Proc.  of  the  17th  Int’l  Conf.  on  Information  Processing  and  Management  of  Uncertainty  in  Knowledge-based  Systems.  Cádiz:
                     Springer, 2018. 272–283. [doi: 10.1007/978-3-319-91479-4_23]
                 [21]   Zhou ZD, Ren ZL, Gao GJ, Jiang H. An empirical study of optimization bugs in GCC and LLVM. Journal of Systems and Software,
                     2021, 174: 110884. [doi: 10.1016/j.jss.2020.110884]
                 [22]   Jimborean A, Loechner V, Clauss P. Handling multi-versioning in LLVM: Code tracking and cloning. In: Proc. of the 2011 Workshop on
                     Intermediate Representations, in Conjunction with CGO (WIR 2011). Chamonix: HAL, 2011.
                 [23]   Moses W, Churavy V. Instead of rewriting foreign code for machine learning, automatically synthesize fast gradients. In: Proc. of the
                     34th Int’l Conf. on Neural Information Processing Systems. Vancouver: Curran Associates Inc., 2020. 1046.
                 [24]   Garba P, Favaro M. SATURN-software deobfuscation framework based on LLVM. In: Proc. of the 3rd ACM Workshop on Software
                     Protection. London: ACM, 2019. 27–38. [doi: 10.1145/3338503.3357721]
                 [25]   Wang AJ, Yi XY, Yan YH. UPIR: Toward the design of unified parallel intermediate representation for parallel programming models. In:
                     Proc.  of  the  2022  Int’l  Conf.  on  Parallel  Architectures  and  Compilation  Techniques.  Chicago:  ACM,  2022.  530–531.  [doi:  10.1145/
                     3559009.3569646]
                 [26]   Ünay E, İnan B, Yiğit E. Supporting custom instructions with the LLVM compiler for RISC-V processor. arXiv:2310.18353, 2023.
                 [27]   Zakowski Y, Beck C, Yoon I, Zaichuk I, Zaliva V, Zdancewic S. Modular, compositional, and executable formal semantics for LLVM
                     IR. Proc. of the ACM on Programming Languages, 2021, 5(ICFP): 67. [doi: 10.1145/3473572]
                 [28]   VenkataKeerthy  S,  Aggarwal  R,  Jain  S,  Desarkar  MS,  Upadrasta  R,  Srikant  YN.  IR2VEC:  LLVM  IR  based  scalable  program
                     embeddings. ACM Trans. on Architecture and Code Optimization (TACO), 2020, 17(4): 32. [doi: 10.1145/3418463]
                 [29]   Sarang AD, Choi SH, Park KW. Plotting OSS-based supply chain attack strategies and the defense failure. In: Proc. of the 25th Int’l Conf.
                     on Information Security Applications. Jeju Island: Springer, 2024. 311–323. [doi: 10.1007/978-981-96-1624-4_24]
                 [30]   Lins M, Mayrhofer R, Roland M, Hofer D, Schwaighofer M. On the critical path to implant backdoors and the effectiveness of potential
                     mitigation techniques: Early learnings from XZ. arXiv:2404.08987, 2024.
                 [31]   Agrawal V, Dabral A, Palit T, Shen YM, Ferdman M. Architectural support for dynamic linking. In: Proc. of the 20th Int’l Conf. on
                     Architectural  Support  for  Programming  Languages  and  Operating  Systems.  Istanbul:  ACM,  2015.  691–702.  [doi:  10.1145/2694344.
                     2694392]
                 [32]   von Hagen W. The Definitive Guide to GCC. Apress, 2011.
                 [33]   Chen KJ, Arias O, Deng QX, Oliveira D, Guo XL, Jin YE. FineDIFT: Fine-grained dynamic information flow tracking for data-flow
                     integrity using coprocessor. IEEE Trans. on Information Forensics and Security, 2022, 17: 559–573. [doi: 10.1109/TIFS.2022.3144868]
                 [34]   Horan B. Cross compile environment. In: Horan B, ed. Practical Raspberry Pi. Berkeley: Apress, 2013. 105–124. [doi: 10.1007/978-1-
                     4302-4972-6_6]
                 [35]   x264-benchmark. 2025. https://github.com/wzssyqa/x264-benchmark/tree/no-abs-path
                 [36]   GNU GSL. 2025. https://github.com/wzssyqa/cachebench/tree/gsl
                 [37]   SQLite3 benchmark. 2025. https://github.com/wzssyqa/sqlite-bench/tree/use-system-libsqlite3
                 [38]   KissFFT. 2022. https://github.com/project-gemmi/benchmarking-fft
   42   43   44   45   46   47   48   49   50   51   52