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软件学报 ISSN 1000-9825, CODEN RUXUEW                                        E-mail: jos@iscas.ac.cn
         Journal of Software,2021,32(6):1663−1681 [doi: 10.13328/j.cnki.jos.006243]   http://www.jos.org.cn
         ©中国科学院软件研究所版权所有.                                                          Tel: +86-10-62562563


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         面向 AADL 模型的存储资源约束可调度性分析

                              1
                       2
               1
         陆   寅 ,   秦树东 ,   习乐琪 ,   董云卫  1
         1
          (西北工业大学  计算机学院,陕西  西安  710072)
         2 (西北工业大学  软件学院,陕西  西安  710072)
         通讯作者:  董云卫, E-mail: yunweidong@nwpu.edu.cn

         摘   要:  嵌入式实时系统在安全关键领域变得越来越重要,其广泛应用于航空航天、汽车电子等具有严格时间约
         束的实时系统中.随着嵌入式系统的复杂度越来越高,在系统开发的早期设计阶段就需要对其可调度性进行分析评
         估.系统中的存储资源会对可调度性产生一定影响,在抢占式实时嵌入式系统引入缓存后,任务的最坏执行时间可能
         发生变化.因此,分析缓存相关抢占延迟对实时嵌入式系统的可调度性影响,一直以来是困扰大规模复杂系统架构设
         计的一个技术难题.提出一种面向软件架构级别、基于抢占调度序列的缓存相关抢占延迟计算方法,用来分析缓存
         相关抢占延迟约束下 AADL(架构分析和设计语言)模型的可调度性.扩展了 AADL 关于存储资源架构设计的模型
         元素,来支持对缓存属性进行建模,提出一种基于模型构件进行抢占序列排序、缓存相关抢占延迟时间计算和被抢
         占任务最坏执行时间的估算方法,来对系统架构各功能构件在共享系统存储资源下系统的可调度性进行分析.还实
         现了分析缓存相关抢占延迟约束下的系统任务可调度性分析工具原型,并以某型飞机机载开放式智能信息系统为
         例,在航空电子系统架构设计中进行尝试,验证了该方法的在复杂系统设计中的对实时性分析的可行性.
         关键词:  软件架构分析与设计语言 AADL;复杂嵌入式系统;缓存相关抢占延迟;资源约束的可调度性
         中图法分类号: TP311

         中文引用格式:  陆寅,秦树东,习乐琪,董云卫.面向 AADL模型的存储资源约束可调度性分析.软件学报,2021,32(6):1663−1681.
         http://www.jos.org. cn/1000-9825/6243.htm
         英文引用格式: Lu Y, Qin SD, Xi LQ,  Dong YW. On  schedulability  analysis  of AADL architecture with storage resource
         constraint. Ruan Jian Xue Bao/Journal of Software, 2021,32(6):1663−1681 (in Chinese). http://www.jos.org.cn/1000-9825/6243.htm
         On Schedulability Analysis of AADL Architecture with Storage Resource Constraint

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         LU Yin ,   QIN Shu-Dong ,   XI Le-Qi ,   DONG Yun-Wei 1
         1 (School of Computer Science, Northwest Polytechnical University, Xi’an 710072, China)
         2 (School of Software, Northwest Polytechnical University, Xi’an 710072, China)
         Abstract:    The embedded system has been wildly applied in real-time automatic control systems, and most of these systems are safety-
         critical. For  example, the  engine  control systems in  an  automobile,  and the  avionics in  an  airplane. It is very important to verify the
         schedulability property of such real-time embedded system in its early design stages, so that to avoid unexpected loss for the debugging of
         architecture design frictions.  However, it has been  proved  to be  a tough challenge to evaluate the schedulability of  a  PSRT
         (preemptive-scheduling real-time) system,  especially  when taking the  constraints of system resources into  consideration.  The cache
         memory build inside the processor is such a kind of exclusive-accessing resource that is shared by all the tasks deployed on the processor.
         In addition, the CPRD (cache-related preemption delay) caused by preemptive task scheduling will bring extra time to the execution time
         to all the tasks. Thus, the CPRD should be taken into consideration when estimating the WCET (worst case executing time) of tasks in a

            ∗  基金项目:  国家自然科学基金(61772423)
              Foundation item: National Natural Science Foundation of China (61772423)
              本文由“形式化方法与应用”专题特约编辑田聪教授推荐.
              收稿时间: 2020-08-31;  修改时间: 2020-10-26;  采用时间: 2020-12-19; jos 在线出版时间: 2021-02-07
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