Page 90 - 《软件学报》2026年第6期
P. 90

刘佳玮 等: 面向   RISC-V  架构的深度学习算子测试                                                 2409


                 [28]   Guo  QY,  Xie  XF,  Li  Y,  Zhang  XY,  Liu  Y,  Li  XH.  Audee:  Automated  testing  for  deep  learning  frameworks.  In:  Proc.  of  the  35th
                     IEEE/ACM Int’l Conf. on Automated Software Engineering. Melbourne: IEEE, 2020. 486–498. [doi: 10.1145/3324884.3416571]
                 [29]   Li ZY, Wu JZ, Ling X, Luo TY, Rui ZQ, Wu YJ. The seeds of the FUTURE sprout from history: Fuzzing for unveiling vulnerabilities in
                     prospective deep-learning libraries. In: Proc. of the 47th IEEE/ACM Int’l Conf. on Software Engineering (ICSE). Ottawa: IEEE, 2020.
                     1616–1627. [doi: 10.1109/ICSE55347.2025.00132]
                 [30]   Harzevili NS, Mohajer MM, Wei MS, Pham HV, Wang S. History-driven fuzzing for deep learning libraries. ACM Trans. on Software
                     Engineering and Methodology, 2025, 34(1): 19. [doi: 10.1145/3688838]
                 [31]   Deng YL, Xia CS, Peng HR, Yang CY, Zhang LM. Large language models are zero-shot fuzzers: Fuzzing deep-learning libraries via
                     large  language  models.  In:  Proc.  of  the  32nd  ACM  SIGSOFT  Int’l  Symp.  on  Software  Testing  and  Analysis.  Seattle:  ACM,  2023.
                     423–435. [doi: 10.1145/3597926.3598067]
                 [32]   Deng ZZ, Meng GZ, Chen K, Liu K, Liu T, Xiang L, Chen CY. Differential testing of cross deep learning framework APIs: Revealing
                     inconsistencies and vulnerabilities. In: Proc. of the 32nd USENIX Conf. on Security Symp. Anaheim: USENIX Association, 2023. 414.
                 [33]   Waterman A, Lee Y, Patterson DA, Asanovic K. The RISC-V instruction set manual, volume I: Base user-level ISA. Technical Report,
                     UCB/EECS-2011-62, University of California at Berkeley, 2011.
                 [34]   Celio  C,  Chiu  PF,  Nikolic  B,  Patterson  DA,  Asanović  K.  BOOMv2:  An  open-source  out-of-order  RISC-V  core.  Technical  Report,
                     UCB/EECS-2017-157, University of California at Berkeley, 2017.
                 [35]   Lopoukhine A, Ficarelli F, Vasiladiotis C, Lydike A, van Delm J, Dutilleul A, Benini L, Verhelst M, Grosser T. A multi-level compiler
                     backend  for  accelerated  micro-kernels  targeting  RISC-V  ISA  extensions.  In:  Proc.  of  the  23rd  ACM/IEEE  Int’l  Symp.  on  Code
                     Generation and Optimization. Las Vegas: ACM, 2025. 163–178. [doi: 10.1145/3696443.3708952]
                 [36]   Hussain  T,  Tahir  MW,  Mushtaq  M,  Khalid  S.  Design  and  benchmarking  of  a  low-cost  RISC-V-based  high-performance  computing
                     cluster for edge computing. In: Proc. of the 2025 Int’l Conf. on Energy, Power, Environment, Control and Computing (ICEPECC 2025).
                     Gujrat: IET, 2025. 579–586. [doi: 10.1049/icp.2025.1168]
                 [37]   Titopoulos V, Alexandridis K, Peltekis C, Nicopoulos C, Dimitrakopoulos G. Optimizing structured-sparse matrix multiplication in RISC-V
                     vector processors. IEEE Trans. on Computers, 2025, 74(4): 1446–1460. [doi: 10.1109/TC.2025.3533083]
                 [38]   Kovač M, Dragić L, Malnar B, Minervini F, Palomar O, Rojas C, Olivieri M, Knezović J, Kovač M. FAUST: Design and implementation
                     of a pipelined RISC-V vector floating-point unit. Microprocessors and Microsystems, 2023, 97: 104762. [doi: 10.1016/j.micpro.2023.
                     104762]
                 [39]   Lee Y, Waterman A, Cook H, Zimmer B, Keller B, Puggelli A, Kwak J, Jevtic R, Bailey S, Blagojevic M, Chiu PF, Avizienis R, Richards
                     B, Bachrach J, Patterson D, Alon E, Nikolic B, Asanovic K. An agile approach to building RISC-V microprocessors. IEEE Micro, 2016,
                     36(2): 8–20. [doi: 10.1109/MM.2016.11]
                 [40]   Xie XF, Liang Z, Gu P, Basak A, Deng L, Liang L, Hu X, Xie Y. SpaceA: Sparse matrix vector multiplication on processing-in-memory
                     accelerator. In: Proc. of the 2021 IEEE Int’l Symp. on High-performance Computer Architecture (HPCA). Seoul: IEEE, 2021. 570–583.
                     [doi: 10.1109/HPCA51647.2021.00055]
                 [41]   Cavalcante M, Schuiki F, Zaruba F, Schaffner M, Benini L. Ara: A 1-GHz+ scalable and energy-efficient RISC-V vector processor with
                     multiprecision  floating-point  support  in  22-nm  FD-SOI.  IEEE  Trans.  on  Very  Large  Scale  Integration  (VLSI)  Systems,  2020,  28(2):
                     530–543. [doi: 10.1109/TVLSI.2019.2950087]
                 [42]   Gautschi M, Schiavone PD, Traber A, Loi I, Pullini A, Rossi D, Flamand E, Gürkaynak FK, Benini L. Near-threshold RISC-V core with
                     DSP  extensions  for  scalable  IoT  endpoint  devices.  IEEE  Trans.  on  Very  Large  Scale  Integration  (VLSI)  Systems,  2017,  25(10):
                     2700–2713. [doi: 10.1109/TVLSI.2017.2654506]
                 [43]   Chen TQ, Moreau T, Jiang ZH, Zheng LM, Yan D, Cowan M, Shen HC, Wang LY, Hu YW, Ceze L, Guestrin C, Krishnamurthy A.
                     TVM:  An  automated  end-to-end  optimizing  compiler  for  deep  learning.  In:  Proc.  of  the  13th  USENIX  Conf.  on  Operating  Systems
                     Design and Implementation. Carlsbad: USENIX Association, 2018. 578–594.
                 [44]   David R, Duke J, Jain A, Reddi Vj, Jeffries N, Li J, Kreeger N, Nappier I, Natraj M, Wang TZ, Warden P, Rhodes R. TensorFlow lite
                     micro: Embedded machine learning for tinyML systems. Proc. of Machine Learning and Systems, 2021, 3: 800–811.

                 附中文参考文献
                  [1]   刘畅, 武延军, 吴敬征, 赵琛. RISC-V 指令集架构研究综述. 软件学报, 2021, 32(12): 3992–4024. http://www.jos.org.cn/1000-9825/
                     6490.htm [doi: 10.13328/j.cnki.jos.006490]
                  [3]   韩金池, 王智栋, 马浩, 宋威. Spike-FlexiCAS: 支持缓存架构灵活配置的 RISC-V 处理器模拟器. 软件学报, 2025, 36(9): 3954–3969.
   85   86   87   88   89   90   91   92   93   94   95