Page 225 - 《软件学报》2021年第6期

软件学报 ISSN 1000-9825, CODEN RUXUEW E-mail: jos@iscas.ac.cn
Journal of Software,2021,32(6):1799−1817 [doi: 10.13328/j.cnki.jos.006250] http://www.jos.org.cn
©中国科学院软件研究所版权所有. Tel: +86-10-62562563

∗
芯片开发功能验证的形式化方法

1,2
1,2
1,2
1,2
1,2
姚广宇 , 张 南 , 田 聪 , 段振华 , 刘灵敏 , 孙风津 1,2
1
(西安电子科技大学 计算理论与技术研究所,陕西 西安 710071)
2 (综合业务网理论及关键技术国家重点实验室(西安电子科技大学),陕西 西安 710071)
通讯作者: 张南, E-mail: nanzhang@xidian.edu.cn; 田聪, E-mail: ctian@mail.xidian.edu.cn; 段振华, E-mail: zhhduan@mail.xidian.edu.cn

摘 要: 在芯片设计领域,采用模型驱动的 FPGA 设计方法是目前较为安全可靠的一种方法.但是,基于模型驱动
的 FPGA 设计需要证明 FPGA 设计模型和生成 Verilog/VHDL 代码的一致性;同时,芯片设计的正确性、可靠性和安
全性也至关重要.目前,多采用仿真方法对模型和代码的一致性进行验证,很难保证设计的可靠性和安全性,并存在
验证效率低、工作量大等问题.提出一种新型验证设计模型和生成代码一致性的方法,该方法利用 MSVL 语言进行
系统建模,并通过模型提取命题投影时序逻辑公式描述的系统的性质,通过统一模型检测的原理,验证模型是否满足
性质的有效性.进而,应用信号灯控制电路系统作为验证实例,对验证方法做了检验和说明.
关键词: 芯片设计;模型驱动;功能一致性;MSVL 建模;命题投影时序逻辑
中图法分类号: TP311

中文引用格式: 姚广宇,张南,田聪,段振华,刘灵敏,孙风津.芯片开发功能验证的形式化方法.软件学报,2021,32(6):1799−1817.
http://www.jos.org.cn/1000-9825/6250.htm
英文引用格式: Yao GY, Zhang N, Tian C, Duan ZH, Liu LM, Sun FJ. Formal method of functional verification for chip
development. Ruan Jian Xue Bao/Journal of Software, 2021,32(6):1799−1817 (in Chinese). http://www.jos.org.cn/1000-9825/
6250.htm
Formal Method of Functional Verification for Chip Development

1,2
1,2
1,2
1,2
1,2
YAO Guang-Yu , ZHANG Nan , TIAN Cong , DUAN Zhen-Hua , LIU Ling-Min , SUN Feng-Jin 1,2
1 (Institute of Computing Theory and Technology, Xidian University, Xi’an 710071, China)
2 (State Key Laboratory of Integrated Services Networks (Xidian University), Xi’an 710071, China)
Abstract: In the field of chip design, the use of model-driven FPGA design methods is currently a safer and more reliable method.
However, model-driven FPGA design needs to prove the consistency of the FPGA design model and the generated Verilog/VHDL code.
Further, the chip design correctness, performance, reliability, and safety are critical. At present, simulation methods are often used to
verify the consistency of models and codes. It is difficult to ensure the reliability and safety of the design, and there are problems such as
low verification efficiency and heavy workload. This study proposes a new method to verify the consistency of the design model and the
generated code. This method uses the MSVL language to model the system, and propositional projection temporal logic (PPTL) formula
to describe the properties of the system, then based on the principle of unified model checking, verifies whether the model meets the
validity of the property. Furthermore, a signal light control system is used as a verification example to verify and explain the verification
method.
Key words: chip design; model-driven; functional consistency; MSVL modeling; propositional projection temporal logic

∗ 基金项目: 国家重点研发计划(2018AAA0103202); 国家自然科学基金(61751207, 61732013); 陕西省重点科技创新团队
(2019TD-001)
Foundation item: National Key Research and Development Program of China (2018AAA0103202); National Natural Science
Foundation of China (61751207, 61732013); Key Science and Technology Innovation Team of Shaanxi Province(2019TD-001)
本文由“形式化方法与应用”专题特约编辑姜宇副教授推荐.
收稿时间: 2020-08-30; 修改时间: 2020-10-26; 采用时间: 2020-12-19; jos 在线出版时间: 2021-02-07